The present invention relates to a semiconductor integrated circuit device, and particularly to art that can be effectively adapted to a semiconductor integrated circuit device that employs a master slice system.
In a semiconductor integrated circuit device employing a master slice system, signal wirings of a plurality of layers make connections in standard cells and among the standard cells that are regularly arranged in the form of a matrix. Though the functions and arrangement of the standard cells are nearly fixed, the connection pattern of the signal wirings can be modified for every logic that is required. That is, employment of a master slice system makes it possible to develop a various kinds of semiconductor integrated circuit devices in short periods of time only by modifying the connection pattern.
In a semiconductor integrated circuit device employing a master slice system, the connection pattern of the signal wirings is formed by an automatic arranging/routing system (DA: Design Automation) assisted by a computer. The automatic arranging/routing system carries out the following processing.
First, based on logic circuit diagrams that are designed, the logic circuit data are input in the automatic arranging/routing system.
Next, the automatic arranging/routing system arranges a standard cell pattern stored in the base data as a fixed pattern on the semiconductor integrated circuit device (base chip) that is virtually illustrated. Then, based upon the logic circuit data, the connection pattern of the logic circuit is arranged according to the arrangement of the basic cell pattern (wirings in the standard cells). The connection pattern of the logic circuit constitutes the logic circuit or part of the logic circuit. The connection pattern of the logic circuit is automatically arranged by the automatic arranging/routing system.
Next, the automatic arranging/routing system connects the individual logic circuits via the signal wirings to complete a logic circuit to be mounted on the semiconductor integrated circuit device. The signal wiring is automatically arranged on wiring channel regions. In the wiring channel regions, virtual X-Y lattices (called X-Y mesh) are employed. The X-Y lattices comprise two sets of lattice elements which cross each other at right angles and which have equal lattice intervals. The signal wirings are set along the X-Y lattices by the automatic arranging/routing system.
Then, the logic data completed by the automatic arranging/routing system are converted by the automatic arranging/routing system into data for preparing a mask based on design rules, e.g., device process rules that determine the widths of the signal wirings, minimum gaps among the wirings, and so on.
A mask for connection is formed by, for example, an electron beam lithography device based on the data for preparing the mask. Using the mask for connection, the device processing is carried out to complete a semiconductor integrated circuit device mounting a predetermined logic.
In the semiconductor integrated circuit device which employs the master slice system, the signal wiring of two layers, for example, constitute a connection pattern. Of the two layers of the wirings, the first layer extends in X-direction with the wirings thereof being arranged at equal intervals in the Y-direction perpendicular to the X-direction. The second layer extends in the Y-direction includes a plurality of wirings arranged at equal intervals in the X-direction. The signal wirings of the first and second layers are electrically connected to each other at their crossing portions through connection holes formed in an interlayer insulating film between the first and second layers of the signal wirings. The signal wirings are made of an aluminum alloy, for example.
The portions where the first and second layers are connected together constitute so-called dog bones. The word "dog bone" stands for a shape of the wiring having square portions which are wider than the wiring portions and where the connection holes are formed in order to provide margins for mask alignment between the first and second layers in the step of fabrication.
The semiconductor integrated circuit device employing the master slice system is disclosed in, for example, Japanese Patent Laid-open No. 34039/1985.